Signal processing systems that perform a "sum of products" operation on digitally encoded signals are widely used in various filtering and signal conditioning applications. The object of these systems is to process digitally encoded and weighted signals to produce an analog output. The signal processing entails multiplying the digital input signals, summing the results of the intermediate multiplication procedures, and producing an analog output.
The "sum of products" operation can be defined for one or more signal groups. In the case of two signal groups, the "sum of products" expression is given as: ##EQU1## where
C is the final result (or system output);
A.sub.i is the i.sup.th signal from signal group A, where A is a group containing n.sub.a signals, each signal being m.sub.a bits long, and thus having resolution of m.sub.a bits;
B.sub.j is the j.sup.th signal from signal group B, where B is a group containing n.sub.b signals, each signal being m.sub.b bits long, and thus having a resolution of m.sub.b bits;
and, .gamma..sub.i,j is a constant or scale factor for the product of the i.sup.th signal from group A and the j.sup.th signal from group B.
Further, each element of the signal group A is represented as a weighted sum of m.sub.a bits and may be expressed as: ##EQU2## where a.sub.i,k is the k.sup.th bit which has a value of plus or minus one in the case of a bipolar coding scheme, and zero or one in the case of a unipolar coding scheme, and .alpha..sub.k is the weight of the k.sup.th bit.
Similarly, the signal group B is represented as a weighted code of m.sub.b bits and may be expressed as: ##EQU3## where b.sub.j,l is the l.sup.th bit which has a value of plus or minus one in the case of a bipolar coding scheme, and zero or one on the case of a unipolar coding scheme, and .beta..sub.l is the weight of the l.sup.th bit.
Thus, the result, or system output, may be expressed as: ##EQU4##
Several approaches to designing a digital multiplier accumulator to perform the necessary computations are widely used in the art. One approach is a mostly analog approach, characterized in that the digitally encoded signals are first converted to analog signals, through the use of a D/A converter or equivalent. These analog signals are then multiplied and summed in the analog domain, to produce the desired sum of products output. The analog multiplication may be achieved via either Gilbert cell or transconductance amplifier based techniques, while the addition may be accomplished through the use of traditional amplifier techniques.
The mostly analog approach yields a design with a relatively high operational speed; however, there are significant disadvantages. First, such an approach consumes a relatively high amount of power. Second, since this approach is very heavily dependent on analog circuitry, the performance of this approach is limited due to the inherently unstable nature (drift) of analog circuitry. The accuracy of the analog approach is typically in the range of 1 to 5%, with 1% being the limit of state of the art technology.
An alternative approach is the mostly digital approach, characterized in that it utilizes only digital processing elements. The digitally encoded signals are multiplied using well known digital multiplication techniques. The individual multiplication results are then summed using digital adders, to produce the system output which is the "sum of products."
The mostly digital approach is plagued by several disadvantages. First, due to the inherent computational delays within the digital multipliers and adders, this approach results in a relatively low operational speed. Second, due to the complexity of the digital processing elements used, this approach also consumes a relatively high amount of power. Also, in the digital approach, a digital to analog stage must be used in order to convert the digital result to an analog output.
Accordingly, it is an object of the present invention to provide a digital multiplier accumulator suitable for low power, high speed operation.
Another object of the present invention is to perform a digital multiplier accumulator operation within a time period corresponding to a single logic element delay.
It is another object of the present invention to provide a highly integrated digital multiplier accumulator, realized with standard Complementary Metal Oxide Semiconductor (CMOS) logic technology and thin film resistor technology.
Still another object of the present invention is the provision of a highly integrated digital multiplier accumulator achieved using Application Specific Integrated Circuit (ASIC) technology.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious to those skilled in the art from the description itself, and further will be appreciated by those practicing the invention and using the resulting digital multiplier accumulator.
In accordance with the present invention, the signals used in the multiplication and addition operations are broken down into sign and magnitude components. Since the sign component is limited in the number of input and output states that may be assumed, a digital logic implementation is conveniently used to perform the multiplication of the sign portion. The computation of the magnitude portion and the multiplication of the magnitude and sign portions of the signal is implemented with the use of a network of resistors that connect the output of the digital logic sign portion to the processing element output.